Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-18
Freescale Semiconductor
To change from FEI clock mode to FBI clock mode, follow this procedure:
1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the
system clock source.
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
reference clock has been appropriately selected.
6.5.2
Using a 32.768 kHz Reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor
of 512, the DCO output (MCGOUT) frequency is 16.78 MHz at high-range. If the DRS[1:0] bits are set
to %01, the multiplication factor is doubled to 1024, and the resulting DCO output frequency is 33.55 Mhz
at mid-range. If the DRS[1:0] bits are set to %10, the multiplication factor is set to 1536, and the resulting
DCO output frequency is 50.33 Mhz at high-range. Make sure that the resulting bus clock frequency does
not exceed the maximum specified bus clock frequency of the device.
Setting the DMX32 bit in MCGC4 to 1 increases the FLL multiplication factor to allow the 32.768 kHz
reference to achieve its maximum DCO output frequency. When the DRS[1:0] bits are set to %00, the
32.768 kHz reference can achieve a high-range maximum DCO output of 19.92 MHz with a multiplier of
608. When the DRS[1:0] bits are set to %01, the 32.768 kHz reference can achieve a mid-range maximum
DCO output of 39.85 MHz with a multiplier of 1216. When the DRS[1:0] bits are set to %10, the 32.768
kHz reference can achieve a high-range maximum DCO output of 59.77 MHz with a multiplier of 1824.
Make sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
In FBI and FEI modes, setting the DMX32 bit is not recommended. If the internal reference is trimmed to
a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the
microcontroller system clock out of specification and damage the part.
6.5.3
MCG Mode Switching
When switching between operational modes of the MCG, certain configuration bits must be changed to
properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS, CLKS,
or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or OSCINIT) must
be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the
mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001
(divide-by-2) or %010 (divide -by-4) to divide the external reference down to the required frequency
between 1 and 2 MHz.
If switching to FBE or FEE mode, first setting the DIV32 bit ensures a proper reference frequency is sent
to the FLL clock at all times.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor
between 512, 1024, and 1536 with the DRS[1:0] bits in MCGC4. Writes to the DRS[1:0] bits is ignored if
LP=1 or PLLS=1.
