Rapid GPIO (RGPIO)
10-8
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
Figure 10-7. RGPIO Toggle Data Register (RGPIO_TOG)
10.4
Functional Description
The RGPIO module is a relatively-simple design with its behavior controlled by the program-visible
registers defined within its programming model.
The RGPIO module is connected to the processor’s local two-stage pipelined bus with the stages of the
ColdFire core’s operand execution pipeline (OEP) mapped directly onto the bus. This structure allows the
processor access to the RGPIO module for single-cycle pipelined reads and writes with a zero wait-state
response (as viewed in the system bus data phase stage).
10.5
Initialization Information
The reset state of the RGPIO module disables the entire 16-bit data port. Prior to using the RGPIO port,
software typically:
•
Enables the appropriate pins in RGPIO_ENB
•
Configures the pin direction in RGPIO_DIR
•
Defines the contents of the data register (RGPIO_DATA)
10.6
Application Information
This section examines the relative performance of the RGPIO output pins for two simple applications
•
The processor executes a loop to toggle an output pin for a specific number of cycles, producing a
square-wave output
•
The processor transmits a 16-bit message using a three-pin SPI-like interface with a serial clock,
serial chip select, and serial data bit.
In both applications, the relative speed of the GPIO output is presented as a function of the location of the
output bit (RGPIO versus peripheral bus GPIO).
Offset: RGPI 0xE (RGPIO_TOG)
Access: Write-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
TOG
Reset
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—
—
—
—
—
—
—
—
—
—
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Table 10-10. RGPIO_TOG Field Descriptions
Field
Description
15–0
TOG
Toggle data.
0 No effect
1 Inverts the corresponding bit in RGPIO_DATA
