Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-15
26
Reserved, must be cleared.
25
BFHBR
BDM force halt on BDM reset. Determines operation of the device after a BDM reset. This bit is cleared after a
power-on reset and is unaffected by any other reset.
0 The device enters normal operation mode following a BDM reset.
1 The device enters in halt mode following a BDM reset, as if the BKGD pin was held low after a power-on-reset
or standard BDM-initiated reset.
Note:
This bit can only change state if XCSR[ENBDM] = 1 and the flash is unsecure.
24
BDFR
Background debug force reset. Forces a BDM reset to the device. This bit always reads as 0 after the reset has
been initiated.
0 No reset initiated.
1 Force a BDM reset.
23
PSTBH
PST trace buffer halt. Indicates if the processor is halted due to the PST trace buffer being full when recording in
a obtrusive mode.
0 PST trace buffer not full
1 CPU halted due to PST trace buffer being full in obtrusive mode
22–21
PSTBST
PST trace buffer state. Indicates the current state of the PST trace buffer recording.
00 PSTB disabled
01 PSTB enabled and waiting for the start condition
10 PSTB enabled, recording and waiting for the stop condition
11 PSTB enabled, completed recording after the stop condition was reached
20
Reserved, must be cleared.
19–16
D1HRL
Debug 1-pin hardware revision level. Indicates the hardware revision level of the 1-pin debug module implemented
in the ColdFire core. For this device, this field is 0x1.
15–8
PSTBWA
PST trace buffer write address. Indicates the current write address of the PST trace buffer. The most significant
bit of this field is sticky; if set, it remains set until a PST/DDATA reset event occurs. As the ColdFire core inserts
PST and DDATA packets into the trace buffer, this field is incremented. The value of the write address defines the
next location in the PST trace buffer to be loaded. In other words, the contents of PSTB[PSTBWA-1] is the last
valid entry in the trace buffer.
The msb of this field can be used to determine if the entire PST trace buffer has been loaded with valid data.
The PSTBWA is unaffected when a buffer stop condition has been reached, the buffer is disabled, or a system
reset occurs. This allows the contents of the PST trace buffer to be retrieved after these events to assist in debug.
Note:
Since this device contains a 64-entry trace buffer, PSTBWA[6] is always zero.
7
PSTBR
PST trace buffer reset. Generates a reset of the PST trace buffer logic, which clears PSTBWA and PSTBST. The
same resources are reset when a disabled trace buffer becomes enabled and upon the receipt of a BDM GO
command when operating in obtrusive trace mode. These reset events also clear any accumulation of PSTs. This
bit always reads as a zero.
0 Do not force a PST trace buffer reset
1 Force a PST trace buffer reset
Table 20-9. CSR2 Field Descriptions (continued)
Field
Description
PSTBWA[7]
PSTB Valid Data Locations
(Oldest to Newest)
0
0, 1, ... PSTBWA-1
1
PSTBWA, 1,..., 0, 1, PSTBWA-1
