Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-48
Freescale Semiconductor
monitoring as the execution of this command is considerably less obtrusive to the real-time operation of
an application than a BACKGROUND/read-PC/GO command sequence.
20.4.1.5.18
WRITE_CREG
If the processor is halted, this command writes the 32-bit operand to the selected control register. This
register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor control
registers are always 32-bits wide, regardless of implemented register width. The register is addressed
through the core register number (CRN). See
for the CRN details when CRG is 11.
If the processor is not halted, this command is rejected as an illegal operation and no operation is
performed.
20.4.1.5.19
WRITE_DREG
This command writes the 32-bit operand to the selected debug control register. This grouping includes all
the debug control registers ({X}CSR
n
, BAAR, AATR, TDR, PBR
n
, PBMR, AB
x
R, DBR, DBMR).
Accesses to debug control registers are always 32-bits wide, regardless of implemented register width. The
register is addressed through the core register number (CRN). See
for CRN details.
NOTE
When writing XCSR, CSR2, or CSR3, WRITE_DREG only writes
bits 23–0. The upper byte of these debug registers is only written with the
special WRITE_XCSR_BYTE, WRITE_CSR2_BYTE, and
WRITE_CSR3_BYTE commands.
Write CPU control register
Active Background
0xC0+CRN
CREG data
[31–24]
CREG data
[23–16]
CREG data
[15–8]
CREG data
[7–0]
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
Write debug control register
Non-intrusive
0x80+CRN
DREG data
[31–24]
DREG data
[23–16]
DREG data
[15–8]
DREG data
[7–0]
host
→
target
host
→
target
host
→
target
host
→
target
host
→
target
D
L
Y
