NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Device Overview
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 1-9
1.4.2 System Clocks
Table 1-5 describes each of the system clocks.
1.4.3 Clock Gating
To save power, peripheral clocks can be shut off by programming the system clock gating registers. For
details, refer to
Section 5.7.10, “System Clock Gating Control 1 Register (SCGC1) .”
Table 1-5. System Clocks
Clock Description
OSCOUT This is the direct output of the external oscillator module and can be selected as the real-time
counter clock source. This signal is used by the Real Time Counter, and the MCG. See
Chapter 6,
“Multipurpose Clock Generator (MCG) ” and Chapter 12, “Real-Time Counter (RTC) ,” for details.
MCGOUT This clock drives the CPU, debug, RAM, and BDM directly and is divided by two to clock all
peripherals (BUSCLK). Control bits in the MCG control registers determine which of three clock
sources is connected:
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) or phase-locked loop (PLL) output
See
Chapter 6, “Multipurpose Clock Generator (MCG) ,” for details on configuring the MCGOUT
clock.
MCGLCLK This clock source runs at half the rate of the low frequency DCO (digitally controlled oscillator).
Development tools can select this internal self-clocked source to speed up BDC communications in
systems where the bus clock is slow. Please see
Figure 6-1 , Figure 20-2 , and their accompanying
text for details.
MCGERCLK This is the external reference clock and can be selected as an alternate clock for the ADC.
MCGIRCLK This is the internal reference clock and can be selected as the real-time counter clock source.
MCGFFCLK This is the fixed frequency clock (FFCLK) after being synchronized to the bus clock. It can be
selected as a clock source for the TPM modules. The frequency of the FFCLK is determined by the
settings of the MCG.
LPOCLK This clock is generated from an internal low-power oscillator that is completely independent of the
MCG module. The LPOCLK can be selected as the clock source to the RTC or COP.
TMRCLK1 &
TMRCLK2 Optional external clock sources for the TPMs and MTIMs. These clocks must be limited to
one-quarter the frequency of the bus clock for synchronization.
ADACK (not
shown) The ADC module also has an internally generated asynchronous clock which allows it to run in
STOP mode. This signal is not available externally.
CLKOUT This is an optional output of the device which can be used to deliver the crystal oscillator output or
the output of the PLL off-chip.