Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
5-21
5.7.10
System Clock Gating Control 1 Register (SCGC1)
This register contains control bits to enable or disable the bus clock to three of the timers (MTIM2 is
controlled by SCGC4), ADC, IICs and two of the three SCI modules on the chip. Gating off the clocks to
unused peripherals reduces the microcontroller’s run and wait currents. See
Section 5.6, “Peripheral Clock
for more information.
7
6
5
4
3
2
1
0
R
MTIM1
TPM2
TPM1
ADC
IIC2
IIC1
SCI2
SCI1
W
Reset:
1
1
1
1
1
1
1
1
Figure 5-11. System Clock Gating Control 1 Register (SCGC1)
Table 5-16. SCGC1 Register Field Descriptions
Field
Description
7
MTIM1
MTIM1 Clock Gate Control
0 Bus clock to the MTIM1 module is disabled.
1 Bus clock to the MTIM1 module is enabled.
6
TPM2
TPM2 Clock Gate Control
0 Bus clock to the TPM2 module is disabled.
1 Bus clock to the TPM2 module is enabled.
5
TPM1
TPM1 Clock Gate Control
0 Bus clock to the TPM1 module is disabled.
1 Bus clock to the TPM1 module is enabled.
4
ADC
ADC Clock Gate Control
0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
3
IIC2
IIC2 Clock Gate Control
.
0 Bus clock to the IIC2 module is disabled.
1 Bus clock to the IIC2 module is enabled.
2
IIC1
IIC1 Clock Gate Control
0 Bus clock to the IIC1 module is disabled.
1 Bus clock to the IIC1 module is enabled.
1
SCI2
SCI2 Clock Gate Control
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
1
SCI1
SCI1 Clock Gate Control
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.
