Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-14
Freescale Semiconductor
Figure 6-8. MCG Mode State Diagram
6.4.3
Mode Switching
The IREFS bit can be changed at anytime, but the actual switch to the newly selected clock is shown by
the IREFST bit. When switching between engaged internal and engaged external modes, the FLL or PLL
begins locking again after the switch is completed.
The CLKS bits can also be changed at anytime, but the actual switch to the newly selected clock is shown
by the CLKST bits. If the newly selected clock is not available, the previous clock remains selected.
The DRS bits can be changed at anytime except when LP bit is 1. If the DRS bits are changed while in
FLL engaged internal (FEI) or FLL engaged external (FEE), the bus clock remains at the previous DCO
range until the new DCO starts. When the new DCO starts the bus clock switches to it. After switching to
the new DCO the FLL remains unlocked for several reference cycles. After the selected DCO startup time
is over, the FLL is locked. The completion of the switch is shown by the DRST bits.
For details, see
.
Entered from any state when
the MCU enters Stop mode
Returns to the state that was active before
the MCU entered Stop mode, unless a
reset occurs while in Stop mode.
FEI
FEE
FBE
FBI
PBE
PEE
BLPI
BLPE
Stop
