Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
8-3
type determines whether the program counter placed in the exception stack frame defines the
location of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to be executed.
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1MB boundary. This instruction address is generated by
fetching a 32-bit exception vector from the table located at the address defined in the vector base
register (VBR). The index into the exception table is calculated as (4
×
vector number). After the
exception vector has been fetched, the contents of the vector serves as a 32-bit pointer to the
address of the first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal instruction
processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1-MB address boundary. For the
V1 ColdFire core, the only practical locations for the vector table are based at 0x(00)00_0000 in the flash
or 0x(00)80_0000 in the RAM. The table contains 256 exception vectors; the first 64 are reserved for
internal processor exceptions, and the remaining 192 are device-specific interrupt vectors. The IRQ
assignment table is partially populated depending on the exact set of peripherals for the given device.
The exception vector table for MCF51CN128 series devices is shown in
.
Table 8-2. MC51CN128 Series Exception and Interrupt Vector Table
Vector
Address
Offset
In
te
rru
pt Le
v
e
l
Priority
Ve
c
to
r
Nu
m
b
e
r
Stacked
Program
Counter
Vector Description
Enable
Source
Vector
Name
0x000
N/A
0
—
Initial supervisor stack
pointer
N/A
N/A
Vreset
0x004
N/A
1
—
Initial program counter
N/A
N/A
0x008–
0x0FC
N/A
2–63
—
Reserved for internal CPU
exceptions (see Table 7-6)
7
7-4
Reserved
0x100
7
mid
64
Next
IRQ_pin
IRQ_SC[IRQIE]
IRQ_SC[IRQF]
Virq
0x104
7
3
65
Next
Low_voltage_detect
PMC_LVDIE
PMC_LVDF
Vlvd
PMC_LVWIE
PMC_LVWF
0x108
7
2
66
Next
MCG_lock
MCG_C3[LOLIE]
MCG_SC[LOLS]
Vlol
7
1
Reserved
6
7
Reserved for remapped
vector #1
Vl6p7
6
6
Reserved for remapped
vector #2
Vl6p6
0x10C
6
5
67
Next
TPM1_ch0
TPM1_C0SC[CH0IE]
TPM1_C0SC[CH0F
]
Vtpm1ch0
