NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 5-19
5.7.9 System Power Management Status and Control 3 Register
(SPMSC3)
This register reports the status of the low voltage warning function and selects the low voltage detect trip
voltage. SPMSC3 is not reset when exiting from stop2.
7 6 5 4 3 2 1 0
R
LPR
LPRS
LPWUI
0 PPDF 0
PPDE
1
1
PPDE is a write-once bit that can be used to permanently disable the PPDC bit.
PPDC
W PPDACK
Reset: 0 0 0 0 – 0 1 0
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-13. SPMSC2 Register Field Descriptions
Field Description
7
LPR
Low-Power Regulator Control — The LPR bit controls entry into the low-power run and low-power wait modes
in which the voltage regulator is put into standby. This bit cannot be set if PPDC is set. If PPDC and LPR are set
in a single write instruction, only PPDC is actually set. LPR is cleared when an interrupt occurs in low-power
mode and the LPWUI bit is set.
0 Low-power run and low-power wait modes are disabled.
1 Low-power run and low-power wait modes are requested.
6
LPRS
Low-Power Regulator Status — This read-only status bit indicates that the voltage regulator has entered into
standby for the low-power run or wait mode.
0 The voltage regulator is not currently in standby.
1 The voltage regulator is currently in standby.
5
LPWUI
Low-Power Wake-up on Interrupt — This bit controls if the voltage regulator exits standby when any active
MCU interrupt occurs.
0 The voltage regulator remains in standby on an interrupt.
1 The voltage regulator exits standby on an interrupt. LPR is cleared.
4 Reserved, must be cleared.
3
PPDF
Partial Power-Down Flag — This read-only status bit indicates that the microcontroller has recovered from stop2
mode.
0 Microcontroller has not recovered from stop2 mode.
1 Microcontroller recovered from stop2 mode.
2
PPDACK
Partial Power-Down Acknowledge — Writing 1 to PPDACK clears the PPDF bit.
1
PPDE
Partial Power-Down Enable — The write-once PPDE bit locks the partial power-down feature. This is a
write-once bit.
0 Partial power-down is not enabled.
1 Partial power-down is enabled and controlled by the PPDC bit.
0
PPDC
Partial Power-Down Control — The PPDC bit controls which power-down mode is selected. This bit cannot be
set if LPR is set. If PPDC and LPR are set in a single write instruction, only PPDC is actually set. PPDE must be
set for PPDC to be set.
0 Stop3 low power mode enabled.
1 Stop2 partial power-down mode enabled.