Serial Peripheral Interface (SPI)
MCF51CN128 Reference Manual, Rev. 6
14-4
Freescale Semiconductor
Figure 14-2. SPI Module Block Diagram
14.1.3
SPI Baud Rate Generation
, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
SPI Shift Register
Shift
Clock
Shift
Direction
Rx Buffer
Full
Tx Buffer
Empty
Shift
Out
Shift
In
Enable
SPI System
Clock
Logic
Clock Generator
Bus Rate
Clock
Master/Slave
Mode Select
Mode Fault
Detection
Master Clock
Slave Clock
SPI
Interrupt
Request
Pin Control
M
S
Master/
Slave
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
M
S
S
M
SPIBR
Tx Buffer (Write
SPIxD)
Rx Buffer (Read SPIxD)
