Memory
MCF51CN128 Reference Manual, Rev. 6
4-30
Freescale Semiconductor
4.4.2.6
Flash Command Register (FCMD)
The FCMD register is the flash command register. All FCMD bits are readable and writable during a
command write sequence while bit 7 reads 0 and is not writable.
Table 4-13.
FSTAT Field Descriptions
Field
Description
7
FCBEF
Command Buffer Empty Flag.
The FCBEF flag indicates that the command buffer is empty so that a new
command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF flag has
no effect on FCBEF. Writing a 0 to FCBEF after writing an aligned address to the flash array memory, but before
FCBEF is cleared, aborts a command write sequence and causes the FACCERR flag to set. Writing a 0 to
FCBEF outside of a command write sequence does not set the FACCERR flag. Writing a 1 to this bit clears it.
0 Command buffers are full.
1 Command buffers are ready to accept a new command.
6
FCCF
Command Complete Flag
. The FCCF flag indicates that there are no more commands pending. The FCCF flag
is cleared when FCBEF is cleared and sets automatically after completion of all active and pending commands.
The FCCF flag does not set when an active program command completes and a pending burst program
command is fetched from the command buffer. Writing to the FCCF flag has no effect on FCCF.
0 Command in progress.
1 All commands are completed.
5
FPVIOL
Protection Violation Flag
. The FPVIOL flag indicates an attempt was made to program or erase an address in
a protected area of the flash memory during a command write sequence. Writing a 0 to the FPVIOL flag has no
effect on FPVIOL. Writing a 1 to this bit clears it. While FPVIOL is set, it is not possible to launch a command or
start a command write sequence.
0 No protection violation detected.
1 Protection violation has occurred.
4
FACCERR
Access Error Flag
. The FACCERR flag indicates an illegal access has occurred to the flash memory caused by
either a violation of the command write sequence, issuing an illegal flash command (see
), or the execution of a CPU STOP instruction while a command is executing (FCCF
= 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. Writing a 1 to this bit clears it. While FACCERR
is set, it is not possible to launch a command or start a command write sequence.
0 No access error detected.
1 Access error has occurred.
3
Reserved, must be cleared.
2
FBLANK
Flag Indicating the Erase Verify Operation Status
. When the FCCF flag is set after completion of an erase
verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is cleared
by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to the
FBLANK flag has no effect on FBLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
1–0
Reserved, must be cleared.
7
6
5
4
3
2
1
0
R
0
FCMD
W
Reset
0
0
0
0
0
0
0
0
Figure 4-9. Flash Command Register (FCMD)
