NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

Page: 130 / 487

Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-18 Freescale Semiconductor
5.7.8 System Power Management Status and Control 2 Register
(SPMSC2)
This register contains status and control bits to configure the low power run and wait modes and configure
the stop mode behavior of the microcontroller. See
Section 3.7.2, “Low-Power Wait Mode (LPwait),” for
more information.
SPMSC2 is not reset when exiting from STOP2.
7 6 5 4 3 2 1 0
R LVDF
1
0
LVDIE LVDRE
2
LVDSE LVDE
2
0
BGBE
W LVDACK
Reset: 0 0 0 1 1 1 0 0
1
LVDF is set when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
2
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-8. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field Description
7
LVDF
Low-Voltage Detect Flag — The LVDF bit indicates the low-voltage detect event status.
0 Low-voltage warning is not present.
1 Low-voltage warning is present or was present.
6
LVDACK
Low-Voltage Detect Acknowledge — If LVDF is set, a low-voltage condition has occurred. To acknowledge this
low-voltage detection, write 1 to LVDACK, which automatically clears LVDF if the low-voltage detection is no
longer present.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF is set.
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset (if
LVDE is set).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE
Low-Voltage Detect Stop Enable — If LVDE is set, this read/write bit determines if the low-voltage detect
function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.