Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-3
concurrent operation of the processor and BDM-initiated memory commands. In addition, the
option is provided to allow interrupts to occur. See
Section 20.4.2, “Real-Time Debug Support”
.
•
Program trace support—The ability to determine the dynamic execution path through an
application is fundamental for debugging. The V1 solution implements a trace buffer that records
processor execution status and data, which can be subsequently accessed by the external emulator
system to provide program (and optional partial data) trace information. See
.
There are two fields in debug registers which provide revision information: the hardware revision level in
CSR and the 1-pin debug hardware revision level in CSR2.
summarizes the various debug
revisions.
20.1.2
Features
The Version 1 ColdFire debug definition supports the following features:
•
Classic ColdFire functionality mapped into the single-pin BDM interface
•
Real time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be
configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
•
Capture of compressed processor status and debug data into on-chip trace buffer provides program
(and optional slave bus data) trace capabilities
•
On-chip trace buffer provides programmable start/stop recording conditions plus support for
obtrusive or PC-profiling modes
•
Debug resources are accessible via single-pin BDM interface or the privileged WDEBUG
instruction from the core
20.1.3
Modes of Operations
V1 ColdFire devices typically implement a number of modes of operation, including run, wait, and stop
modes. Additionally, the operation of the core’s debug module is highly dependent on a number of chip
configurations which determine its operating state.
When operating in secure mode, as defined by a 2-bit field in the flash memory examined at reset, BDM
access to debug resources is extremely restricted. It is possible to tell that the device has been secured, and
Table 20-1. Debug Revision Summary
Revision
CSR[HRL]
CSR2[D1HRL]
Enhancements
A
0000
N/A
Initial ColdFire debug definition
B
0001
N/A
BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
SYNC_PC command to display the processor’s current PC
B+
1001
N/A
Added 3 PC breakpoint registers PBR1–3
CF1_B+
1001
0001
Converted to HCS08 1-pin BDM serial interface
Added PST compression and on-chip PST/DDATA buffer for program trace
