Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-56
Freescale Semiconductor
20.4.2
Real-Time Debug Support
The ColdFire family supports debugging real-time applications. For these types of embedded systems, the
processor must continue to operate during debug. The foundation of this area of debug support is that while
the processor cannot be halted to allow debugging, the system can generally tolerate the small intrusions
with minimal effect on real-time operation.
NOTE
The details regarding real-time debug support will be supplied at a later
time.
20.4.3
Trace Support
For the baseline V1 ColdFire core and its single debug signal, support for trace functionality is completely
redefined. The V1 solution provides an on-chip PST/DDATA trace buffer (known as the PSTB) to record
the stream of PST and DDATA values.
As a review, the classic ColdFire debug architecture supports real-time trace via the PST/DDATA output
signals. For this functionality, the following apply:
•
One (or more) PST value is generated for each executed instruction
•
Branch target instruction address information is displayed on all non-PC-relative change-of-flow
instructions, where the user selects a programmable number of bytes of target address
— Displayed information includes PST marker plus target instruction address as DDATA
— Captured address creates the appropriate number of DDATA entries, each with 4 bits of address
•
Optional data trace capabilities are provided for accesses mapped to the slave peripheral bus
— Displayed information includes PST marker plus captured operand value as DDATA
— Captured operand creates the appropriate number of DDATA entries, each with 4 bits of data
The resulting PST/DDATA output stream, with the application program memory image, provides an
instruction-by-instruction dynamic trace of the execution path.
Even with the application of a PST trace buffer, problems associated with the PST bandwidth and
associated fill rate of the buffer remain. Given that there is one (or more) PST entry per instruction, the
PSTB would fill rapidly without some type of data compression.
Consider the following example to illustrate the PST compression algorithm. Most sequential instructions
generate a single PST = 1 value. Without compression, the execution of ten sequential instructions
generates a stream of ten PST = 1 values. With PST compression, the reporting of any PST = 1 value is
delayed so that consecutive PST = 1 values can be accumulated. When a PST
≠
1 value is reported, the
maximum accumulation count is reached, or a debug data value is captured, a single accumulated PST
value is generated. Returning to the example with compression enabled, the execution of ten sequential
instructions generates a single PST value indicating ten sequential instructions have been executed.
This technique has proven to be effective at significantly reducing the average PST entries per instruction
and PST entries per machine cycle. The application of this compression technique makes the application
of a useful PST trace buffer for the V1 ColdFire core realizable. The resulting 5-bit PST definitions are
shown in
.
