Serial Peripheral Interface (SPI)
MCF51CN128 Reference Manual, Rev. 6
14-12
Freescale Semiconductor
MOSI output pin from a master and the MISO
waveform applies to the MISO output from a slave. The SS
OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The
master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back
high at the end of the eighth bit time of the transfer. The SS In waveform applies to the slave select input
of a slave.
Figure 14-9. SPI Clock Formats (CPHA = 1)
When CPHA is set, the slave begins to drive its MISO output when SS goes to active low, but the data is
not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter
onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both
the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA is set, the slave’s SS input is not required to go to its inactive
high level between transfers.
shows the clock formats when CPHA is cleared. At the top of the figure, the eight bit times
are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the
last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the
Bit Time #
(Reference)
MSB First
LSB First
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
Sample In
(MISO Or MOSI)
MOSI
(Master Out)
MISO
(Slave Out)
SS Out
(Master)
SS In
(Slave)
Bit 7
Bit 0
Bit 6
Bit 1
Bit 2
Bit 5
Bit 1
Bit 6
Bit 0
Bit 7
1
2
6
7
8
...
...
...
