Serial Peripheral Interface (SPI)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
14-13
setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies
for a specific transfer, depending on the value in CPOL. The Sample In waveform applies to the MOSI
input of a slave or the MISO input of a master. The MOSI
waveform applies to the MOSI output pin from
a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The SS In waveform applies to the slave select input of a slave.
Figure 14-10. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA is cleared, the slave’s SS input must go to its inactive high level between
transfers.
14.5.2
SPI Interrupts
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
Bit Time #
(Reference)
MSB First
LSB First
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
Sample In
(MISO Or MOSI)
MOSI
(Master Out)
MISO
(Slave Out)
SS Out
(Master)
SS In
(Slave)
Bit 7
Bit 0
Bit 6
Bit 1
Bit 2
Bit 5
Bit 1
Bit 6
Bit 0
Bit 7
1
2
6
7
8
...
...
...
