Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-57
Table 20-26. CF1 Debug Processor Status Encodings
PST[4:0]
Definition
0x00
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST with this encoding.
0x01
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock
cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
0x02
Reserved
0x03
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
0x04
Begin execution of PULSE and WDDATA instructions. PULSE defines triggers or markers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a
value of 0x04 is signaled on the PST port, followed by the appropriate marker, and then the data transfer
on the DDATA port. The number of captured data bytes depends on the WDDATA operand size.
0x05
Begin execution of taken branch or SYNC_PC BDM command. For some opcodes, a branch target
address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins
the data output. This encoding also indicates that the SYNC_PC command has been processed.
0x06
Reserved
0x07
Begin execution of return from exception (RTE) instruction.
0x08–0x0B Indicates the number of data bytes to be loaded into the PST trace buffer. The capturing of peripheral
bus data references is controlled by CSR[DDC].
0x08 Begin 1-byte data transfer on DDATA
0x09 Begin 2-byte data transfer on DDATA
0x0A Reserved
0x0B Begin 4-byte data transfer on DDATA
0x0C–0x0F Indicates the number of address bytes to be loaded into the PST trace buffer. The capturing of branch
target addresses is controlled by CSR[BTB].
0x0C Reserved
0x0D Begin 2-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[16:1])
0x0E Begin 3-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[23:1])
0x0F Reserved
0x10–0x11 Reserved
0x12
Completed execution of 2 sequential instructions
0x13
Completed execution of 3 sequential instructions
0x14
Completed execution of 4 sequential instructions
0x15
Completed execution of 5 sequential instructions
0x16
Completed execution of 6 sequential instructions
0x17
Completed execution of 7 sequential instructions
0x18
Completed execution of 8 sequential instructions
0x19
Completed execution of 9 sequential instructions
0x1A
Completed execution of 10 sequential instructions
