Parallel Input/Output Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
9-4
9.2
Pin Controls
This section shows the superset of pin control functions which may be present on V1 ColdFire devices.
Some devices may not include all of these controls. See the summary table earlier in the chapter for
specific capabilities for your device. See
Section 2.3, “Pin Mux Controls
” for information on Pin Mux
Control registers.
9.2.1
Pin Controls Overview
A set of registers (shown in
) control pull-ups, slew rate, drive strength and input filter enables
for the pins. They may also be used in conjunction with the peripheral functions on these pins. These
registers are associated with the parallel I/O ports and Rapid GPIO (RGPIO) ports, but operate
independently of both.
Figure 9-1. Pin Control Logic Block Diagram
9.2.2
Pin Controls Programming Model
These registers control the pull-ups, slew rate, drive strength, and input filter for all the pins and may be
used for the peripheral functions (FEC, Mini-FlexBus, etc.) on these pins.
IPb
u
s
PTxPE[n]
Port Pull-up Enable
Read xPE
Write xPE
PTxDS[n]
Port Drive Strength Control
Write xDS
Read xDS
PTxSE[n]
Port Slew Rate Control
Write xSE
Read xSE
PTxIFE[n]
Port Input Filter Enable
Write xIFE
Read xIFE
