Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
17-23
17.4.4.2
FAST ACK and NACK
To improve reliability and communication robustness, implementation of Packet Error Checking (PEC) by
SMBus devices is optional for SMBus devices but required for devices participating in and only during
the Address Resolution Protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on
all the message bytes. The PEC is appended to the message by the device that supplied the last data byte.
If the PEC is present but not correct, a NACK is issued by receiver. Otherwise, an ACK is issued. In order
to calculate the CRC-8 by software, this module can hold SCL line to low after receiving eighth SCL (bit
8th) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent out to
the bus by setting or clearing TXAK bit if FASK (fast ACK/NACK enable bit) is enabled.
SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable
devices presence on the bus (battery, docking station, etc.). Besides to indicate a slave device busy
condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or
data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices
have the ability to generate the not acknowledge after the transfer of each byte and before the completion
of the transaction. This is important because SMBus does not provide any other resend signaling. This
difference in the use of the NACK signaling has implications on the specific implementation of the SMBus
port, especially in devices that handle critical system data such as the SMBus host, and the SBS
components.
NOTE
In the last byte of master receive slave transmit mode, the master should
send NACK to bus so FACK should be switched off before the last byte
transmit.
17.5
Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
17.6
Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
occur, provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine.
Determine the interrupt type by reading the status register. For SMBus timeouts interrupt, the interrupt is
driven by SLTF and masked with bit IICIE. The SLTF bit must be cleared by software by writing a 1 to it
in the interrupt routine. Determine the interrupt type by reading the status register.
