Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-16
Freescale Semiconductor
5.7.5
System Options Register 3 (SOPT3)
This register controls the output mux functions of the PHYCLK and CLKOUT pins. The various clock
sources must be enabled/disabled by the appropriate controls elsewhere in the device.
5.7.6
System Device Identification Register (SDIDH, SDIDL)
These read-only registers identify the ColdFire derivative. This allows the development software to
recognize where specific memory blocks, registers, and control bits are located in a target microcontroller.
Table 5-8. SOPT2 Field Descriptions
Field
Description
7
RSVD
Reserved. must be cleared.
6–5
FC
Flash Configuration
— These bits specify the amount of flash memory available on this device.
00 64 KB Memory Map
01 Reserved
10 96 KB Memory Map
11 128 KB Memory Map
4–0
PMC_LVD_TRIM
Reserved, must be cleared.
7
6
5
4
3
2
1
0
R
0
0
0
CS
PCS
W
Reset:
0
0
0
0
0
0
0
0
Figure 5-5. System Options Register 3 (SOPT3)
Table 5-9. SOPT3 Field Descriptions
Field
Description
7-5
Reserved, must be cleared.
4-2
CS
CLKOUT Select
000 Disabled
001 OSCOUT
010 MCGOUT
011 BUSCLK
100 LPOCLK
Others Reserved
1-0
PCS
Phy Clock Select
00 Disabled
01 OSCOUT
10 MCGOUT
11 BUSCLK
