NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

Page: 241 / 487

Mini-FlexBus
Freescale Semiconductor 11-4
MCF51CN128 Reference Manual, Rev. 6
11.3.1 Chip-Select Address Registers (CSAR0 – CSAR1)
The CSAR n registers specify the chip-select base addresses.
NOTE
The only applicable address range for which the chip-selects can be active
are 0x(00)40_0000 – 0x(00)7F_FFFF. Set the CSAR
n and CSMR n registers
appropriately before accessing this region.
11.3.2 Chip-Select Mask Registers (CSMR0 – CSMR1)
CSMR n registers specify the address mask and allowable access types for the respective chip-selects.
Table 11-2. Mini-FlexBus Chip Select Memory Map
Offset Register
Width
(bits)
Access Reset Value
Section/
Page
0x00
0x0C
Chip-Select Address Register (CSAR n )
n = 0 – 1
32 R/W 0x0000_0000 11.3.1/11-4
0x04
0x10 Chip-Select Mask Register (CSMR n )
n = 0 – 1
32 R/W 0x0000_0000 11.3.2/11-4
0x08
0x14 Chip-Select Control Register (CSCR n )
n = 0 – 1
32 R/W See Section 11.3.3/11-5
Address: 0x00 (CSAR0)
0x0C (CSAR1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-1. Chip-Select Address Registers (CSAR n )
Table 11-3. CSAR n Field Descriptions
Field Description
31–16
BA
Base address. Defines the base address for memory dedicated to chip-select FB_CS n . BA is compared to
bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
15–0 Reserved, must be cleared.
Address: 0x04 (CSMR0)
0x10 (CSMR1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BAM
0 0 0 0 0 0 0
WP
0 0 0 0 0 0 0
V
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-2. Chip-Select Mask Registers (CSMR n )