Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
17-15
17.3.12 IIC Programmable Input Glitch Filter (IICFLT)
Table 17-10. IICFLT Field Descriptions
7
6
5
4
3
2
1
0
R
0
0
0
0
FLT3
FLT2
FLT1
FLT0
W
Reset
0
0
0
0
0
0
0
0
=
Unimplemented or Reserved
Field
Description
3:0
FLT
IIC Programmable Filter Factor contains the programming controls for the width of glitch (in terms of bus clock
cycles) the filter
should absorb; in other words, the filter does not let glitches less than or equal to this width setting pass.
FLT[3:0]
0000 No Filter / Bypass
0001 Filter glitches up to width of 1 (half) IPBUS clock cycle
0010 Filter glitches up to width of 2 (half) IPBUS clock cycles
0011 Filter glitches up to width of 3 (half) IPBUS clock cycles
0100 Filter glitches up to width of 4 (half) IPBUS clock cycles
0101 Filter glitches up to width of 5 (half) IPBUS clock cycles
0110 Filter glitches up to width of 6 (half) IPBUS clock cycles
0111 Filter glitches up to width of 7 (half) IPBUS clock cycles
1000 Filter glitches up to width of 8 (half) IPBUS clock cycle
1001 Filter glitches up to width of 9 (half) IPBUS clock cycles
1010 Filter glitches up to width of 10 (half) IPBUS clock cycles
1011 Filter glitches up to width of 11 (half) IPBUS clock cycles
1100 Filter glitches up to width of 12 (half) IPBUS clock cycles
1101 Filter glitches up to width of 13 (half) IPBUS clock cycles
1110 Filter glitches up to width of 14 (half) IPBUS clock cycles
1111 Filter glitches up to width of 15 (half) IPBUS clock cycles
NOTE: If the filter input clock is connected to 2X IPBUS clock, then the (half) affects the width of glitches
