Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-44
Freescale Semiconductor
20.4.1.5.9
READ_CREG
If the processor is halted, this command reads the selected control register and returns the 32-bit result.
This register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor
control registers are always 32-bits wide, regardless of implemented register width. The register is
addressed through the core register number (CRN). See
for the CRN details when CRG is 11.
If the processor is not halted, this command is rejected as an illegal operation and no operation is
performed.
20.4.1.5.10
READ_DREG
This command reads the selected debug control register and returns the 32-bit result. This register
grouping includes the CSR, XCSR, CSR2, and CSR3. Accesses to debug control registers are always
32-bits wide, regardless of implemented register width. The register is addressed through the core register
number (CRN). See
for CRN details.
Read CPU control register
Active Background
0xE0+CRN
CREG data
[31-24]
CREG data
[23-16]
CREG data
[15-8]
CREG data
[7-0]
host
→
target
D
L
Y
target
→
host
target
→
host
target
→
host
target
→
host
Read debug control register
Non-intrusive
0xA0+CRN
DREG data
[31-24]
DREG data
[23-16]
DREG data
[15-8]
DREG data
[7-0]
host
→
target
D
L
Y
target
→
host
target
→
host
target
→
host
target
→
host
