Timer/PWM Module (TPM)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
19-20
19.6.2.2.1
Input Capture Events
When a channel is configured as an input capture channel, the ELSnB:ELSnA bits select if channel pin is
not controlled by TPM, rising edges, falling edges, or any edge as the edge that triggers an input capture
event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step
sequence described in
Section 19.6.2, “Description of Interrupt Operation
.”
19.6.2.2.2
Output Compare Events
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described in
Section 19.6.2, “Description of Interrupt Operation
.”
19.6.2.2.3
PWM End-of-Duty-Cycle Events
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter
matches the channel value register that marks the end of the active duty cycle period. When the channel is
configured for center-aligned PWM, the timer count matches the channel value register twice during each
PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle
period when the timer counter matches the channel value register. The flag is cleared by the two-step
sequence described in
Section 19.6.2, “Description of Interrupt Operation
.”
