Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-19
20.3.7
Trigger Definition Register (TDR)
TDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug
module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured
as one- or two-level trigger. TDR[31–16] defines the second-level trigger, and TDR[15–0] defines the
first-level trigger.
NOTE
The debug module has no hardware interlocks. To prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR (clear TDR[L2EBL,L1EBL]) before defining triggers.
Table 20-13. AATR Field Descriptions
Field
Description
31–16
Reserved, must be cleared.
15
RM
Read/write mask. Masks the R bit in address comparisons.
14–13
SZM
Size mask. Masks the corresponding SZ bit in address comparisons.
12–11
TTM
Transfer type mask. Masks the corresponding TT bit in address comparisons.
10–8
TMM
Transfer modifier mask. Masks the corresponding TM bit in address comparisons.
7
R
Read/write. R is compared with the R/W signal of the processor’s local bus.
6–5
SZ
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
4–3
TT
Transfer type. Compared with the local bus transfer type signals. These bits also define the TT encoding for
BDM memory commands.
00
Normal processor access
Else Reserved
2–0
TM
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information
for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
000 Reserved
001 User-mode data access
010 User-mode code access
011 Reserved
100 Reserved
101 Supervisor-mode data access
110 Supervisor-mode code access
111 Reserved
