Memory
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
4-21
Recall that ColdFire has a big endian byte addressable memory architecture. The most significant byte of
each address is the lowest numbered as shown in
. Multi-byte operands (e.g., 16-bit words and
32-bit longwords) are referenced using an address pointing to the most significant (first) byte.
0
0
0
0
0
0
0
WP
0
0
0
0
0
0
0
V
0x(FF)FF_E814
MB
MBCSCR1
0
0
0
0
0
0
0
0
0
0
ASET
RDAH
WRAH
WS
MUX
AA
PS
0
0
0
0
0
0
Address
Peripheral
Register
Bit 15/7
14/6
13/5
12/4
11/3
10/2
9/1
Bit 8/0
0x(FF)FF_FFCC
INTC
INTC_ORMR
0
0
0
0
0
0
0
FECDO
0x(FF)FF_FFCD
0
0
SCI3DO
0
0
0
0
0
Address
Peripheral
Register
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_FFD3
INTC
INTC_FRC
0
LVL1
LVL2
LVL3
LVL4
LVL5
LVL6
LVL7
0x(FF)FF_FFD8
INTC
INTC_PL6P7
0
0
REQN
0x(FF)FF_FFD9
INTC
INTC_PL6P6
0
0
REQN
0x(FF)FF_FFDB
INTC
INTC_WCR
ENB
0
0
0
0
MASK
0x(FF)FF_FFDE
INTC
INTC_SFRC
0
0
SET
0x(FF)FF_FFDF
INTC
INTC_CFRC
0
0
CLR
0x(FF)FF_FFE0
INTC
INTC_SWIACK
0
VECN
0x(FF)FF_FFE4
INTC
INTC_LVL1IACK
0
VECN
0x(FF)FF_FFE8
INTC
INTC_LVL2IACK
0
VECN
0x(FF)FF_FFEC
INTC
INTC_LVL3IACK
0
VECN
0x(FF)FF_FFF0
INTC
INTC_LVL4IACK
0
VECN
0x(FF)FF_FFF4
INTC
INTC_LVL15ACK
0
VECN
0x(FF)FF_FFF8
INTC
INTC_LVL6IACK
0
VECN
0x(FF)FF_FFFC
INTC
INTC_LVL7IACK
0
VECN
Table 4-3. Detailed Peripheral Memory Map (continued)
