Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
17-21
17.4.3
Address Matching
All received Addresses can be requested in 7-bit or 10-bit address. IIC Address Register 1, which contains
IIC primary slave address, always participates the address matching process. If the GCAEN bit is set,
general call participates the address matching process. If the ALERTEN bit is set, alert response
participates the address matching process. If SIICAEN bit is set, the IIC Address Register 2 participates
the address matching process.
When the IIC responds to one of above mentioned address, it acts as a slave-receiver and the IAAS bit is
set after the address cycle. Software need to read the IICD register after the first byte transfer to determine
which the address is matched.
17.4.4
System Management Bus Specification
SMBus provides a control bus for system and power management related tasks. A system may use SMBus
to pass messages to and from devices instead of tripping individual control lines. Removing the individual
control lines reduces pin count. Accepting messages ensures future expandability.With System
Management Bus, a device can provide manufacturer information, tell the system what its model/part
number is, save its state for a suspend event, report different types of errors, accept control parameters, and
return its status.
17.4.4.1
Timeouts
The TTIMEOUT,MIN parameter allows a master or slave to conclude that a defective device is holding
the clock low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly
recommended that a slave device release the bus (stop driving the bus and let SCL and SDA float high)
when it detects any single clock held low longer than TTIMEOUT,MIN. Devices that have detected this
condition should reset their communication and be able to receive a new START condition in no later than
TTIMEOUT,MAX.
SMBus defines a clock low time-out, TTIMEOUT of 35 ms and specifies TLOW: SEXT as the cumulative
clock low extend time for a slave device and specifies TLOW: MEXT as the cumulative clock low extend
time for a master device.
17.4.4.1.1
SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible.
Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this
problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle
held low longer than a “timeout” value condition. Devices that have detected the timeout condition must
reset the communication. When active master, if the IIC detects that SMBCLK low has exceeded the value
of T
TIMEOUT,MIN
it must generate a stop condition within or after the current data byte in the transfer
process. When slave, upon detection of the T
TIMEOUT,MIN
condition, the IIC shall reset its communication
and be able to receive a new START condition.
