Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-24
Freescale Semiconductor
peripherals reduces the microcontroller’s run and wait currents. See
Section 5.6, “Peripheral Clock
for more information.
5.7.14
SIM Internal Peripheral Select Register (SIMIPS)
This register configures internal peripheral connections which may be routed to more than one location.
7
6
5
4
3
2
1
0
R
1
1
1
MTIM2
MC
MB
FEC
PTJ
W
Reset:
1
1
1
1
1
_
1
1
1 in 80-pin packages, 0 in 64-pin and 48-pin package.
1
_
2
2
1 in 80-pin and 64-pin packages, 0 in 48-pin package.
Figure 5-14. System Clock Gating Control 3 Register (SCGC4)
Table 5-19. SCGC4 Register Field Descriptions
Field
Description
7-5
Reserved, must be set.
4
MTIM2
MTIM2 Clock Gate Control
0 Bus clock to the MTIM2 module is disabled.
1 Bus clock to the MTIM2 module is enabled.
3
MC
Port Mux Control
0 Bus clock to the Port Mux Control module is disabled.
1 Bus clock to the Port Mux Control module is enabled.
This bit can be set to zero when the mux controls are programmed as desired. This bit affects programming of
the mux controls only. The actual data paths to/from pins are unaffected.
2
MB
Mini-FlexBus Clock Gate Control
0 Bus clock to the Mini-FlexBus module is disabled.
1 Bus clock to the Mini-FlexBus module is enabled.
1
FEC
FEC Clock Gate Control
0 Bus clock to the FEC module is disabled.
1 Bus clock to the FEC module is enabled.
0
PTJ
PTJ Clock Gate Control
0 Bus clock to the PTJ module is disabled.
1 Bus clock to the PTJ module is enabled.
7
6
5
4
3
2
1
0
R
0
0
0
0
TPM2
TPM1
MTIM2
MTIM1
W
Reset:
0
0
0
0
0
0
0
0
Figure 5-15. SIM Internal Peripheral Select Register (SIMIPS)
