Memory
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
4-31
4.5
Security
The MCF51CN128 series microcontroller includes circuitry to prevent unauthorized access to the contents
of flash and RAM memory. When security is engaged, BDM access is restricted to the upper byte of the
ColdFire CSR, XCSR, and CSR2 registers. RAM, flash memory, peripheral registers and most of the CPU
register set are not available via BDM. Programs executing from internal memory have normal access to
all microcontroller memory locations and resources.
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01, SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location, NVOPT, are copied from flash
into the working FOPT register in register space. Enable security by programming the NVOPT location
which can be done at the same time the flash memory is programmed. Set NVOPT[SEC01, SEC00] to 10
engage security. The other three combinations disengage security.
After exiting reset, the XCSR[SEC] bit in the ColdFire debug module is set if the device is secured, cleared
otherwise.
You can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security
key. The security key can be written by the CPU executing from internal memory. It cannot be entered
without the cooperation of a secure user program.
Development tools unsecure devices by an alternate BDM-based methodology shown in
Because both RESET and BKGD pins can be reprogrammed by software, a power-on-reset is required to
be certain of obtaining control of the device via BDM, which is a required prerequisite for clearing
security. Other methods (outlined in red in
) can also be used, but may not work under all
circumstances.
This device supports two levels of security. Both restrict BDM communications as outlined above. In
addition, SOPT1[SL] (see
Section 5.7.3, “System Options 1 Register (SOPT1)
”) can be used to
enable/disable off-chip data accesses through the Mini-FlexBus interface. Off-chip op code accesses
through the Mini-FlexBus are always disallowed when security is enabled.
Table 4-14.
FCMD Field Descriptions
Field
Description
7
Reserved, must be cleared.
6–0
FCMD
Flash Command.
Valid flash commands are shown below. Writing any command other than those listed sets
the FACCERR flag in the FSTAT register.
0x05 Erase Verify
0x20 Program
0x25 Burst Program
0x40 Sector Erase
0x41 Mass Erase
