NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 6-11
6.4 Functional Description
6.4.1 MCG Modes of Operation
The MCG operates in one of the modes described in Table 6-10 .
NOTE
The MCG restricts transitions between modes. For the permitted transitions,
see
Section 6.4.2, “MCG Mode State Diagram.”
Table 6-8. MCG Test and Control Register Field Descriptions
Field Description
7:6 Reserved for test, user code should not write 1’s to these bits.
5
DMX32
DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO
frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. See Table 6-9 .
0 DCO has default range of 25%.
1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
4:2 Reserved for test, user code should not write 1’s to these bits.
1:0
DRST
DRS
DCO Range Status — The DRST read bits indicate the current frequency range for the FLL output, DCOOUT.
See Table 6-9 . The DRST bits do not update immediately after a write to the DRS field due to internal
synchronization between clock domains. The DRST bits are not valid in BLPI, BLPE, PBE or PEE mode and it
reads zero regardless of the DCO range selected by the DRS bits.
DCO Range Select — The DRS bits select the frequency range for the FLL output, DCOOUT. Writes to the DRS
bits while the LP or PLLS bit is set are ignored.
00Low range.
01Mid range.
10High range.
11Reserved
Table 6-9. DCO frequency range
1
1
The resulting bus clock frequency should not exceed the maximum specified bus
clock frequency of the device.
DRS DMX32 Reference range FLL factor DCO range
00 0 31.25 - 39.0625 kHz 512 16 - 20 MHz
1 32.768 kHz 608 19.92 MHz
01 0 31.25 - 39.0625 kHz 1024 32 - 40 MHz
1 32.768 kHz 1216 39.85 MHz
10 0 31.25 - 39.0625 kHz 1536 48-60 MHz
1
0 32.768 kHz 50.33 MHz
1
1 32.768 kHz 1824 59.77 MHz
1
11 Reserved