Intel
®
81341 and 81342—Address Translation Unit (PCI-X)
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
166
Order Number: 315037-002US
2.13.19 ATU Subsystem Vendor ID Register - ASVIR
ATU Subsystem Vendor ID Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3.
2.13.20 ATU Subsystem ID Register - ASIR
ATU Subsystem ID Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3.
Table 41. ATU Subsystem Vendor ID Register - ASVIR
Bit
Default
Description
15:0
0000H
Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
PCI
IOP
Attributes
Attributes
15
12
8
4
0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+02CH
Table 42. ATU Subsystem ID Register - ASIR
Bit
Default
Description
15:0
0000H
Subsystem ID - uniquely identifies the add-in board or subsystem.
PCI
IOP
Attributes
Attributes
15
12
8
4
0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+02EH