Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
953
PMON Unit—Intel
®
81341 and 81342
However, execution of this command is conditional upon a cache hit occurring (Event B
). Thus, the cache hit command becomes the “Command Trigger” that
must occur before the memory read events would no longer be counted.
Example 18. How many Event A’s happen before the first Event B is detected
This example demonstrates how to measure the number of times event A occurs before
the first occurrence of event B.
Table 599. Hardware Event Based Event Counting Example
Opcode
Target
Counter
Increment
Event
Decrement
Event
Trigger Event
Write Event Register
0
Event A
None (000h)
Start
0
Immed (000h)
Stop
0
Event B
Sample
0
Immed (000h)
Read Data Register
0
Figure 160. Block Diagram and Waveforms of Time Based Sampling Example
B6301-01