Intel 81341, Developer'S Manual

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Intel
®
81341 and 81342—DDR SDRAM Memory Controller
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
578 Order Number: 315037-002US
7.3.3.3 DDR SDRAM Bank Sizes and Configurations
The DMCU supports a memory subsystem ranging from 128 Mbytes to 4 GBytes. An
ECC or non-ECC system is implemented using x8, or x16 devices. Table 357 illustrates
supported DDR SDRAM configurations when bit 6 of SDCR0 is cleared, whereas
Table 358 illustrates supported DDR SDRAM configurations when bit 6 of SDCR0 is set.
Note:
128 Mbytes DDR memory size is only applicable when the DMCU is setup to 32-bit data
bus width. Otherwise, the minimum DDR2 memory that can be supported with a 64-bit
data bus is 256 MBytes for one bank.
(
Table 357. Supported DDR2 SDRAM Configurations (SDCR0[6] cleared)
DDR2 SDRAM
Technology
DDR SDRAM
Arrangement # Banks
Address Size Leaf Select
Total Memory Size
a
a. Table indicates 64-bit wide memory subsystem sizes. For 32-bit wide memory, the memory subsystem size would be half of that
indicated.
Row Column BA[2] BA[1] BA[0]
512 Mbit
64Mb x 8
1
14 10 n/a
A[28] A[27]
512M
2 1G
32Mb x 16
1
13 10 n/a
A[27] A[26]
256M
2 512M
1 Gbit
128Mb x 8
1
14 10
A[29] A[29] A[27]
1G
2 2G
64Mb x 16
1
13 10
A[28] A[27] A[26]
512M
2 1G
2 Gbit
256Mb x 8
1
15 10
A[30] A[29] A[28]
2G
2 4
128Mb x 16
1
14 10
A[29] A[28] A[27]
1G
2 2G
Table 358. Supported DDR2 SDRAM Configurations (SDCR0[6] set)
DDR2 SDRAM
Technology
DDR SDRAM
Arrangement # Banks
Address Size Leaf Select
Total Memory Size
a
Row Column BA[2] BA[1] BA[0]
512 Mbit
64Mb x 8
1
14 10 n/a
A[14] A[13]
512M
2 1G
32Mb x 16
1
13 10 n/a
A[14] A[13]
256M
2 512M
1 Gbit
128Mb x 8
1
14 10
A[15] A[14] A[13]
1G
2 2G
64Mb x 16
1
13 10
A[15] A[14] A[13]
512M
2 1G
2 Gbit
256Mb x 8
1
15 10
A[15] A[14] A[13]
2G
2 4
128Mb x 16
1
14 10
A[15] A[14] A[13]
1G
2 2G
a. Table indicates 64-bit wide memory subsystem sizes. For 32-bit wide memory, the memory subsystem size would be half of that
indicated.