Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
51
Introduction—Intel
®
81341 and 81342
1.5.6
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the
81341 and 81342. It uses interrupts to notify each system when new data arrives. The
MU has four messaging mechanisms: Message Registers, Doorbell Registers, Circular
Queues, and Index Registers. Each allows a host processor or external PCI device and
the 81341 and 81342 to communicate through message passing and interrupt
generation. The MU in conjunction with the ATU exists as the PCI Interface for PCI
function 0 when function 0 is setup as a RAID Controller.
1.5.7
DDR Memory Controller
The DDR Memory Controller allows direct control of 400/533 MHz DDR2 SDRAM
memory subsystem. It features programmable chip selects and support for error
correction codes (ECC). The DDR Memory Controller is multi-ported with the following
interfaces: south internal bus, DMA controller, north internal bus. The memory
controller interface configuration support includes Unbuffered DIMMs, Registered
DIMMs, and discrete DDR SDRAM devices.
1.5.8
SRAM Memory Controller
The SRAM Memory Controller allows direct control of a 1 MByte single-ported SRAM
memory subsystem. It supports error correction codes (ECC). The SRAM can be used to
store firmware code or for general purpose data storage.
1.5.9
Peripheral Bus Interface
The Peripheral Bus Interface Unit is a data communication path to the Flash memory
components or other peripherals of 81341 and 81342 hardware system. The PBI
includes support for either 8/16 bit devices. To perform these tasks at high bandwidth,
the bus features a burst transfer capability which allows successive 8/16-bit data
transfers.
1.5.10
Performance Monitoring Unit
The Performance Monitoring Unit allows various events on the 81341 and 81342 to be
monitored.
