Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
577
DDR SDRAM Memory Controller—Intel
®
81341 and 81342
Since the DMCU supports DDR SDRAM bursting, the DMCU increments the column
address based on burst length of four for each DDR SDRAM read or write burst. The
DMCU supports sequential and random burst types. Sequential bursting means the
address issued to DDR SDRAM is incremented by the DDR SDRAM device in linear
fashion during burst cycle. Random bursting means that the address issued with every
new command to the DDR SDRAM can be any address in a currently active page.
Note:
The DMCU only supports Sequential Burst Type. For example, Interleaved Burst Type is
not supported by the DMCU.
Table 356. DDR2 SDRAM Address Translation for 2 Gbit (x8) Device (SDCR0[6] set)
MA[14:0] 14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row
A[30]
A[29]
A[28]
A[27]
A[26]
A[25]
A[24]
A[23]
A[22]
A[21]
A[20]
A[19]
A[18]
A[17]
A[16]
Column
-
-
-
-
V
1
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
1.
A10 is used for precharge variations on the read or write command. See
for more details.
2.
For the Leaf Selects, see
