Intel
®
81341 and 81342—DDR SDRAM Memory Controller
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
616
Order Number: 315037-002US
7.3.4.5
DDR ECC Disabled
When software disables ECC, the DMCU does generate the ECC byte for writes, but
does not check the ECC byte for reads.
7.3.4.6
DDR ECC Testing
Section 7.3.4.4, “Scrubbing” on page 615
explains how the software is responsible for
correcting an error in the memory array once it has been detected by the ECC logic.
The DMCU implements the ECTST register providing the programmer the ability to test
error handling software. For write transactions, the ECTST register value is XORed with
the generated ECC. This inverts the bits where the mask is set prior to writing the ECC
to memory. When the DMCU reads the address later, the ECC mismatches and the error
condition occurs (see
Section 7.5, “ECC Interrupts/Error Conditions” on page 621
).
7.3.5
Memory Regions
The DMCU supports two independent memory regions:
• Memory Mapped Register (MMR) Space
• DDR SDRAM Memory Space
The MMR memory space ranges from 1800H t19FFH of the MMR Base
address registers. Software programs the DDR SDRAM memory space by providing a
base address in SDBR and SDUBR, the size and number of DDR SDRAM banks in SBSR,
and the size of the 32-bit region in S32SR when desired.
7.3.6
DDR SDRAM Clocking
The DMCU provides 6 clocks, three positive (
M_CK[2:0]
) and three negative
(
M_CK[2:0]#
), to the DDR SDRAM memory subsystem at the selected DDR SDRAM
command rate. The 72-bit 2-bank unbuffered DDR SDRAM DIMM specification requires
6 clocks to distribute the loading across eighteen x8 DDR SDRAM components.
