Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
569
DDR SDRAM Memory Controller—Intel
®
81341 and 81342
7.3.1.7
DDR SDRAM Control Block
The DDR SDRAM Control Block contains all functionality to process the DDR SDRAM
data accesses per the transactions issued by the DMARB. To process a transaction the
DDR SDRAM Control Block employs several sub-blocks. The sub-blocks include the
Page Control block, DDR SDRAM State Machine and Pipeline Queues, and Error
Correction Logic.
7.3.1.7.1 Page Control Block
The Page Control Block records and maintains the open DDR SDRAM pages. The DMCU
can keep a maximum of eight/sixteen pages open simultaneously (4 or 8 per bank
depending on the memory technology). 81341 and 81342 supports up to two memory
banks, and 1-Gbit/2-Gbit DDR2 memory technology supports up to eight internal
banks. This accounts for a total of sixteen pages when both memory banks are
implemented. 512-bit DDR2 technology supports only four internal banks, which
therefore accounts for a total of eight pages when both memory banks are
implemented. This block keeps track of open pages and determines when the
transactions hit an open page. For more details about the page hit/miss determination,
see
Section 7.3.3.5, “Page Hit/Miss Determination” on page 589
7.3.1.7.2 DDR SDRAM State Machine and Pipeline Queues
Since the DMCU generates error correction codes based on the data, the DMCU is a
pipelined architecture. Pipelining also ensures acceptable AC timings to the memory
interfaces. The DDR SDRAM state machine pipelines DDR SDRAM memory operations
for several clocks.
7.3.1.7.3 Error Correction Logic
The Error Correction Logic generates the ECC code for DDR SDRAM reads and writes.
For reads, this logic compares the ECC codes read with the locally generated ECC code.
When the codes mismatch then the Error Correction Logic determines the error type.
For a single-bit error, this block determines which bit is in error and corrects the error.
For a single-bit or multi-bit error, the Error Correction Logic logs the error in ELOG0 and
ELOG1. See
Section 7.3.4, “DDR Error Correction and Detection” on page 607
for more
details.
