Intel
®
81341 and 81342—DDR SDRAM Memory Controller
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
668
Order Number: 315037-002US
7.8.36.1 Determining DLLRCVEREN Pulse Optimum Location
The pseudo-code listed below provides an algorithm to determine the optimum location
for the DLLRCVEREN pulse with respect to the DQS signals. The rising and falling edges
of the DLLRCVEREN pulse must be placed in the pre-amble and post-amble windows
driven by the DDR2 memory as shown in
. The DLLRCVEREN pulse has a fixed
width. The entire pulse is shifted by controlling the DLLRCVEREN delay value. The basic
goal of the algorithm is to locate the first rising edge of the DQS signal and use the
result to calculate the optimum DLLRCVEREN delay value. Note that the SDRAM
initialization sequence must be executed before executing this algorithm. Refer to
Section 7.3.3.7, “DDR SDRAM Initialization” on page 594
.
The algorithm starts by taking an initial sample of the DQS signal value using a given
DLLRCVEREN delay value. The DQS sample indicates the value of the DQS signal at the
leading edge of the DLLRCVEREN pulse as shown in
. Using the initial DQS
value, the algorithm proceeds to find the rising edge of DQS. The DQS signal rising
edge is searched by shifting the DLLRCVEREN pulse either left or right depending on
the first sampled DQS value. For example, when the first sampled DQS value is '1',
DLLRCVEREN delay is decreased one delay element at a time until the DQS rising edge
is located. And when the first sampled DQS value is '0', the DLLRCVEREN delay is
increased one delay element at a time until the rising edge of DQS is located.
Once a DQS rising edge is located, the algorithm proceeds to verify that this is the first
DQS rising edge. For example, the DQS rising edge found may be the second rising
edge. When it is determined that it is indeed the second DQS rising edge, the
DLLRCVEREN delay is adjusted by subtracting one full MCLK worth of delay from the
current DLLRCVEREN delay value.
At this stage in the algorithm, with the current DLLRCVEREN delay value, the
DLLRCVEREN leading edge must be aligned with the first rising edge of the DQS signal.
To calculate the optimum DLLRCVEREN delay value, MCLK/4 worth of delay must be
subtracted from the current DLLRCVEREN delay value.
After programming the correct DLLRCVEREN delay value, the FIFO must be reset.
SDCR0 bit 07.
Figure 99. DLLRCVREN Optimum Pulse Location
DLLRCVEREN
DQS [8:0]#
Pre-Amble
Post-Amble
B6353-01
