Intel
®
81341 and 81342—Test Logic Unit and Testability
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
1012
Order Number: 315037-002US
20.2.2.15 Exit2-IR State
This is a temporary state.
All test data registers selected by the current instruction retain their previous value
during this state. The instruction does not change while the TAP controller is in this
state.
Transition to next state: When
TMS
is held high during the next rising edge of
TCK
, the
controller enters the Update-IR state and the scanning process terminates. When
TMS
is held low during the next rising edge of
TCK
, the controller re-enters the Shift-IR
state
20.2.2.16 Update-IR State
The instruction shifted into the instruction register is latched onto the parallel output
from the shift-register path on the falling edge of
TCK
. Once latched, the new
instruction becomes the current instruction.
All test data registers selected by the current instruction retain their previous values in
this state.
Transition to next state: When
TMS
remains high on the rising edge of
TCK
, then the
controller moves to the Select-DR state, else the controller moves to the Run-Test/Idle
state.
