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1 OVERVIEW
1.4 High-speed Instruction Processing
1.4
High-speed Instruction Processing
Subset processing
Subset processing can reduce the number of steps or speed up the instruction processing when the device and label
specified by each operand of an instruction satisfy the specified conditions.
Instruction symbols and the number of operands do not change whether subset processing is applicable or not.
Instructions that support subset processing
For the availability of subset processing for each instruction, refer to the following.
Page 2031 Number of Basic Steps and Availability of Subset Processing
Operand condition
The conditions that the operands need to satisfy to enable subset processing are shown.
■
When a device is specified in an operand
The following table lists the conditions that an operand which specifies a device needs to satisfy.
*1 Including the cases where bit numbers, digits, indirect addresses, or index-modified devices are specified
*2 True when U3En\G
, U3En\G
Zn, U3En\HG
, or U3En\HG
Zn is used in the CPU buffer memory access device of the host CPU
module.
*3 True when U3En\HG
or U3En\HG
Zn is used in the CPU buffer memory access device of another CPU module.
■
When the label assigned to a device is specified in an operand
The same conditions as those applicable when a device is specified in an operand apply.
■
When the label assigned to each label area is specified in an operand
When the label assigned to a label area or latch label area is specified in an operand, any instruction which supports subset
processing performs subset processing regardless of the data type of the operand. (Including the cases where bit numbers or
digits are specified.)
Data type of operand
Condition
Bit data
One of the following is satisfied.
• User device
• Host CPU specification of CPU buffer memory access device (excluding index modification to "U3En")
• Other CPU modules specification of fixed scan communication area of CPU buffer memory access device
• File register
• Local device
• Refresh data register
Signed 16-bit data
Unsigned 16-bit data
Signed 32-bit data
Unsigned 32-bit data
One of the following is satisfied.
• User device
• Host CPU specification of CPU buffer memory access device (excluding index modification to "U3En")
• Other CPU modules specification of fixed scan communication area of CPU buffer memory access device
• Index register
• File register
• Local device
• Refresh data register
• Constant (decimal, hexadecimal)
Single-precision real number
One of the following is satisfied.
• User device
• Host CPU specification of CPU buffer memory access device (excluding index modification to "U3En")
• Other CPU modules specification of fixed scan communication area of CPU buffer memory access device
• Index register
• File register
• Local device
• Refresh data register
• Constant (single-precision real number)
Summary of Contents for MELSEC iQ-R Series
Page 1: ...MELSEC iQ R Programming Manual Instructions Standard Functions Function Blocks ...
Page 2: ......
Page 24: ...22 INDEX 2092 INSTRUCTION INDEX 2093 REVISIONS 2104 WARRANTY 2105 TRADEMARKS 2106 ...
Page 34: ...32 MEMO ...
Page 35: ...33 PART 1 PART 1 OVERVIEW This part consists of the following chapter 1 OVERVIEW ...
Page 68: ...66 1 OVERVIEW 1 5 Precautions on Programming MEMO ...
Page 1448: ...1446 14 REDUNDANT SYSTEM INSTRUCTIONS 14 2 Disabling Enabling System Switching MEMO ...
Page 1972: ...1970 33 TIME DATA TYPE FUNCTIONS 33 4 Division MEMO ...
Page 2067: ...APPX Appendix 5 PID Control Program Examples 2065 A 252 Set PID control data for loop 2 ...
Page 2109: ......