Vicruns 2S-0.4G-B, User Manual

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Chapter 6 Description of Function Codes
It is used to set the valid state mode of the digital input terminal.
When it is selected to be active at high level, it is valid when the corresponding DI terminal is
connected to COM, and invalid when disconnected.
When it is selected to be active at low level, the corresponding DI terminal is invalid when con-
nected with COM, and valid when disconnected.
Function
code
Name
Description
(setting range)
Factory
Default
Change
P5-15 AI1 minimum input value 0.00V
～
10.00V 0.00V
☆
P5-16
AI1 minimum input corresponding
setting
-100.0% ～ 100.0% 0.0%
☆
P5-17 AI1 maximum input value 0.00V
～
10.00V 10.00V
☆
P5-18
AI1 maximum input corresponding
setting
-100.0% ～ 100.0% 100.0%
☆
P5-19 AI1 input filter time 0.00s
～
10.00s 0.10s
☆
The above function codes define the relationship between the analog input voltage and the
set value represented by the analog input. When the analog input voltage exceeds the set
maximum input or minimum input range, the other part will be calculated as the maximum
input or minimum input.
When the analog input is current input, 1mA current is equivalent to 0.5V voltage. (AI2 settin-
gs are the same as AI1 settings). In different applications, the nominal value corresponding
to 100% of the analog setting is different, please refer to the description of each application
section for details. The following illustrations illustrate several settings:
Corresponding set value
(frequency, torque)
100.0%
0 V (0 mA)
10 V (20 mA)
AI
-100.0%
0 V (0 mA)
10 V (20 mA)
AI
Corresponding set value
(frequency, torque)
100.0%
Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching Fig.6-5 Schematic diagram of speed loop PI parameter switching
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