Rohde & Schwarz R&S UPP, User Manual

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Remote Control - Fundamentals
R&S
®
UPP
667 User Manual 1411.1055.32 ─ 10
The changes for the status registers for the cascading operating mode are minor, see
also
Chapter 8.7.3.4, "Cascading and Status System" , on page 872.
6.8.3 Status Byte (STB) and Service Request Enable (SRE) Register
The STB is already defined in IEEE 488.2. It gives a rough overview of the device sta-
tus, collecting information from the lower-level registers. So it is comparable with the
CONDition part of an SCPI register and is at the highest level of the SCPI hierarchy. It
is special in that bit 6 acts as the summary bit of all other bits of the status byte.
Reading the STB does not delete its content!
The status byte is read out with the
*STB?
or a Serial Poll.
Associated with the STB is the SRE. The function of the SRE corresponds to that of
the ENABle part of the SCPI registers. Each bit of the STB is assigned a bit in the
SRE. Bit 6 of the SRE is ignored. If a bit is set in the SRE and the associated bit in the
STB changes from 0 to 1, a service request (SRQ) will be generated on the IEC/IEEE
bus or Ethernet, which triggers an interrupt in the controller configured for this purpose,
and can be further processed by the controller.
The SRE can be set with the
*SRE
command and read out with
*SRE?
.
Reading the EVENt deletes the associated bit in the status byte register (e.g.
STAT:OPER:EVEN?
deletes the OPER bit (d7) in the OPERation register).
Table 6-3: Meaning of bits in status byte
Bit no. Meaning
7 OPERation status register summary bit
This bit is set if an EVENt bit is set in the OPERation status register and the associated ENABle
bit is set to 1.
A set bit indicates that the device is executing an action. The type of action can be determined by
querying the OPERation status register with
STATus:OPERation:CONDition?
or
STATus:OPERation[:EVENt]?
.
6 MSS bit (master status summary bit)
This bit is set if the device triggers a service request. This is the case if one of the other bits of
this register is set together with its mask bit in the service request enable register.
5 ESB bit
Summary bit of the event status register. This bit is set if one of the bits in the event status regis-
ter is set and enabled in the event status enable register.
A set bit indicates an error or event that can be specified more precisely by querying the event
status register by the command
*ESR? .
4 MAV bit (message available)
This bit is set if there is a readable message is in the output buffer. A measurement result or
response to a query (i.e. IEC/IEEE bus command with '?') is present and can be read.
Status Reporting System