Renesas H8S/2158, User Manual

Page: 114 / 929

Section 3 MCU Operating Modes
Rev. 3.00 Jan 25, 2006 page 60 of 872
REJ09B0286-0300
Bit Bit Name Initial Value R/W Description
3 FLSHE 0 R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers of power-down states (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on-
chip peripheral modules (BCR2, WSCR2, PCSR,
SYSCR2).
0: Control registers of power-down states and on-
chip peripheral modules are accessed in an area
from H'(FF)FF80 to H'(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H'(FF)FF80 to H'(FF)FF87.
2 — 0 R/(W) Reserved
The initial value should not be changed.
1
0 ICKS1
ICKS0 0
0 R/W Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, see section 13.3.4, Timer Control
Register (TCR).
3.3 Operating Mode Descriptions
3.3.1 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1. However, because this LSI has a maximum of 18 address output pins,
an external address space can be accessed only when the I/O strobe function of the
AS
/
IOS
pin,
the CP/CF extension function, and the
CS256
function are used.
In extended mode, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an
address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions
as a data bus, and parts of port 9 carry bus control signals. Port 6 functions as a data bus when the
ABW bit in WSCR is cleared to 0.