Renesas H8S/2158, User Manual

Page: 178 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 124 of 872
REJ09B0286-0300
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
6.5.2 Valid Strobes
Table 6.9 shows the data buses used and valid strobes for each access space.
In a read, the
RD
signal is valid for both the upper and lower halves of the data bus. In a write, the
HWR
signal is valid for the upper half of the data bus, and the
LWR
signal for the lower half.
Table 6.9 Data Buses Used and Valid Strobes
Area
Access
Size Read/
Write
Address
Valid
Strobe Upper Data Bus
(D15 to D8) Lower Data
Bus (D7 to D0)
Byte Read —
RD
Valid Ports or others 8-bit access
space
Write —
HWR
Ports or others
Byte Read Even
RD
Valid Invalid 16-bit access
space
Odd Invalid Valid
Write Even
HWR
Valid Undefined
Odd
LWR
Undefined Valid
Word Read —
RD
Valid Valid
Write —
HWR
,
LWR
Valid Valid
Notes: Undefined : Undefined data is output.
Invalid : Input state with the input value ignored.
Ports or others : Used as ports or I/O pins for on-chip peripheral modules, and are not
used as the data bus.