Renesas H8S/2158, User Manual

Page: 192 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 138 of 872
REJ09B0286-0300
6.7.2 Valid Strobes
Table 6.10 shows the data buses used and valid strobes.
Table 6.10 Data Buses Used and Valid Strobes
Access
Size Read/
Write
Address
C C C CPCS1 PCS1 PCS1 PCS1
Pin
CPCS2 CPCS2 CPCS2 CPCS2
Pin
Valid
Strobe Upper Data Bus
(D15 to D8) Lower Data
Bus (D7 to D0)
Byte Read Even L H CPOE Invalid Valid
(even data)
Odd L H Invalid Valid
(odd data)
Write Even L H CPWE Undefined Valid
(even data)
Odd L H Undefined Valid
(even data)
Word Read — L L CPOE Valid (odd data) Valid
(even data)
Write — L L CPWE Valid (odd data) Valid
(even data)
Notes: Undefined: Undefined data is output.
Invalid: Input state with the input value ignored.
6.7.3 Basic Operation Timing
The memory card interface is basically specified as having 3 access states. Figure 6.17 shows the
access timing in memory card mode. The strobe signal waveform for the rising edge and falling
edge at address output can be moved one state by setting the OWEAC and OWENC bits in BCR,
respectively. In this case, wait states must be inserted. For 2-state access, clear both the OWEAC
and OWENC bits to 0. In addition, note that in 3-state access, set the OWEAC and OWENC bits
to B'01 or B'10. Figure 6.18 shows the access timing in memory card mode when the OWEAC and
OWENC bits are set to 1 simultaneously.