Renesas H8S/2158, User Manual

Page: 196 / 929

Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 142 of 872
REJ09B0286-0300
Table 6.11 shows the pin states in an idle cycle.
Table 6.11 Pin States in Idle Cycle
Pins Pin State
A17 to A0 Contents of immediately following bus cycle
D15 to D0 High impedance
AS
,
IOS
,
CS256
,
CPCS1
,
CPCS2
High
RD
,
CPOE
High
HWR
,
LWR
,
CPWE
High
6.9 Bus Arbitration
The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters—the
CPU, DTC, and RFU—that perform read/write operations when they have possession of the bus.
6.9.1 Bus Master Priority
Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal
to the bus master making the request at the designated timing. If there are bus requests from more
than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled. The order of priority of the bus masters is as follows:
(High) RFU > DTC > CPU (Low)