Renesas H8S/2158, User Manual

Page: 699 / 929

Section 19 Multimedia Card Interface (MCIF)
Rev. 3.00 Jan 25, 2006 page 645 of 872
REJ09B0286-0300
19.3.12 Card Status Register (CSTR)
CSTR indicates the MCIF status during command sequence execution.
Bit Bit Name Initial Value R/W Description
7 BUSY 0 R Command Busy
Indicates command execution status. When the
CMDOFF bit in OPCR is set to 1, this bit is
cleared to 0 because the MCIF command
sequence is aborted.
0: Command sequence has ended.
1: Command sequence execution in progress.
6 FIFO_FULL 0 R FIFO Full
Indicates whether receive data FIFO full has
been detected.
0: Receive data FIFO full is not detected.
1: Receive data FIFO full is detected.
After FIFO full detection, this bit is cleared to 0
when resuming to receive read data from the
MMC or when the command sequence ends.
5 FIFO_EMPTY 0 R FIFO Empty
Indicates whether transmit data FIFO empty has
been detected.
0: Transmit data FIFO empty is not detected.
1: Transmit data FIFO empty is detected.
After FIFO empty detection, this bit is cleared to
0 when resuming to transmit data to the MMC or
when the command sequence ends.
4 CWRE 0 R Command Register Write Enable
Indicates whether the CMDR command is being
transmitted or has been transmitted.
0: The CMDR command has been transmitted,
or the START bit in CMDSTRT has not been
set yet, so the new command can be written.
1: The CMDR command is waiting for
transmission or is being transmitted. If the
new command is written, a malfunction will
result.