Renesas H8S/2158, User Manual

Page: 826 / 929

Section 27 Power-Down Modes
Rev. 3.00 Jan 25, 2006 page 772 of 872
REJ09B0286-0300
27.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
SYSCR2, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR)
must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register
(STCR).
•
Standby control register (SBYCR)
•
Low power control register (LPWRCR)
•
System control register 2 (SYSCR2)
•
Module stop control register H (MSTPCRH)
•
Module stop control register L (MSTPCRL)
•
Sub-chip module stop control register BH (SUBMSTPBH)
•
Sub-chip module stop control register BL (SUBMSTPBL)
27.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode, subactive mode, or
watch mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode
1: Shifts to watch mode or high-speed mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.