Section 8 RAM-FIFO Unit (RFU)
Rev. 3.00 Jan 25, 2006 page 174 of 872
REJ09B0286-0300
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
BUD2
BUD1
BUD0
1
1
0
R/W
R/W
R/W
Boundary 2 to 0
These bits select the FIFO size and the
existence of boundary overflow.
000: 32 bytes
001: 64 bytes
010: 128 bytes
011: 256 bytes
100: 512 bytes
101: 1024 bytes
110: 2048 bytes
111: Boundary is not set
Legend:
X: Don't care
Table 8.1 shows how to make settings for BAR, RAR, WAR, and TMP.
In BAR, the bits upper than the boundary become valid depending on the number of FIFO bytes
set in the BUD2 to BUD0 bits. Since the lower bits become invalid, 0 should be written to these
bits. In RAR, WAR, and TMP, the bits lower than the boundary become valid. Since the upper bits
become invalid, 0 should be written to these bits.
Table 8.1
Valid Bits in BAR, RAR, WAR, and TMP
Number of
FIFO Bytes
BAR Valid
Section
BAR Invalid
Section
(Should be
set to 0)
Invalid Sections
in RAR, WAR, and TMP
(Should be set to 0,
no carry)
Valid Sections
in RAR, WAR,
and TMP
32 bytes
A19 to A5
A4
A10 to A5
A4 to A0
64 bytes
A19 to A6
A5 and A4
A10 to A6
A5 to A0
128 bytes
A19 to A7
A6 to A4
A10 to A7
A6 to A0
256 bytes
A19 to A8
A7 to A4
A10 to A8
A7 to A0
512 bytes
A19 to A9
A8 to A4
A10 and A9
A8 to A0
1024 bytes
A19 to A10
A9 to A4
A10
A9 to A0
2048 bytes
A19 to A11
A10 to A4
—
A10 to A0
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...