Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 604 of 872
REJ09B0286-0300
The bus driver/receiver on the port unit and the USB function core process the electrical signal and
signal bit stream on the USB bus line. The token, acknowledge type, and data byte are extracted,
and the acknowledge and data byte are converted to electrical signals of the bit stream (no. 1 and 2
in table 18.4).
In a SETUP token reception, if a GetDescriptor or SetDescriptor command or a device class
specific command is received, the SETUP and EP0OTS flags are set to 1 and SETUP token
reception is informed to the slave CPU (no. 3 in table 18.4). The received command must be
transferred using the FIFO and be interpreted and processed in the slave CPU (no. 6 in table 18.4).
The remaining transactions in the control transfer must also be processed in the slave CPU using
FIFOs (no. 4 and 5 in table 18.4).
In a control transfer, interrupt transfer, and bulk transfer, an IN or OUT token reception is not
informed to the CPU and data transfer is performed continuously. In an IN transaction, transmit
data is prepared in the FIFO in advance and transmission is initiated if the EPTE bit is set;
otherwise a NAK handshaking is performed. After an IN transaction has been completed, transfer
normal completion or abnormal completion is determined by the host handshaking and this result
is informed to the CPU through the TS and TF bits in USBIFR0, the EPTS bit in TSFR0, and the
EPTF bit in TFFR0. In an OUT transaction, an ACK handshaking is performed if the FIFO has
received all data items; otherwise an NAK handshaking is performed. In an IN or OUT
transaction, a STALL handshaking is performed if the endpoint is specified as a STALL state by
EPSTL.
18.4.2
Operation on Receiving a SETUP Token (Endpoint 0)
Transactions sequentially initiated when the host has received a SETUP token are called control
transfer. The control transfer is comprised of three stages: setup, data, and status stages. The
control transfer includes two transfer types: control write transfer and control read transfer. The
transfer type such as control write or read transfer and the number of bytes to be transferred in the
data stage are determined by the 8-byte command transferred by an OUT transaction in setup
stage.
The setup stage comprises a SETUP transaction. The data stage comprises no transaction or one or
multiple data transactions. The status stage comprises a data transaction.
Table 18.5 shows the packets included in each transaction.
Summary of Contents for H8S/2158
Page 10: ...Rev 3 00 Jan 25 2006 page viii of lii...
Page 36: ...Rev 3 00 Jan 25 2006 page xxxiv of lii B Product Lineup 863 C Package Dimensions 864 Index 865...
Page 47: ...Rev 3 00 Jan 25 2006 page xlv of lii Appendix Figure C 1 Package Dimensions TBP 112A 864...
Page 54: ...Rev 3 00 Jan 25 2006 page lii of lii...
Page 70: ...Section 1 Overview Rev 3 00 Jan 25 2006 page 16 of 872 REJ09B0286 0300...
Page 118: ...Section 3 MCU Operating Modes Rev 3 00 Jan 25 2006 page 64 of 872 REJ09B0286 0300...
Page 126: ...Section 4 Exception Handling Rev 3 00 Jan 25 2006 page 72 of 872 REJ09B0286 0300...
Page 198: ...Section 6 Bus Controller Rev 3 00 Jan 25 2006 page 144 of 872 REJ09B0286 0300...
Page 326: ...Section 10 8 Bit PWM Timer PWM Rev 3 00 Jan 25 2006 page 272 of 872 REJ09B0286 0300...
Page 440: ...Section 15 Watchdog Timer WDT Rev 3 00 Jan 25 2006 page 386 of 872 REJ09B0286 0300...
Page 606: ...Section 17 I 2 C Bus Interface IIC Rev 3 00 Jan 25 2006 page 552 of 872 REJ09B0286 0300...
Page 742: ...Section 19 Multimedia Card Interface MCIF Rev 3 00 Jan 25 2006 page 688 of 872 REJ09B0286 0300...
Page 750: ...Section 21 D A Converter Rev 3 00 Jan 25 2006 page 696 of 872 REJ09B0286 0300...
Page 768: ...Section 22 A D Converter Rev 3 00 Jan 25 2006 page 714 of 872 REJ09B0286 0300...
Page 770: ...Section 23 RAM Rev 3 00 Jan 25 2006 page 716 of 872 REJ09B0286 0300...
Page 824: ...Section 26 Clock Pulse Generator Rev 3 00 Jan 25 2006 page 770 of 872 REJ09B0286 0300...
Page 844: ...Section 27 Power Down Modes Rev 3 00 Jan 25 2006 page 790 of 872 REJ09B0286 0300...
Page 878: ...Section 28 List of Registers Rev 3 00 Jan 25 2006 page 824 of 872 REJ09B0286 0300...
Page 926: ...Index Rev 3 00 Jan 25 2006 page 872 of 872 REJ09B0286 0300...